Hardware Electronics Design Engineer

CONTEXT:

• Hardware Project Lead in a multidisciplinary team, in the highly regulated automotive industry. Led the hardware adaptation and industrialization of 5 EPS (Electrical Power Supply) projects in a built-to-print context for American and Japanese clients. Volume: 50k-200k parts/year/project, defect rate < 100 PPM.
• MAIN MISSIONS:
• Manage PCB layouts with a strong focus on high-current routing and thermal dissipation (trace sizing, vias, MOSFET RDson optimization).
• Lead the Design for Manufacturing (DfM) process, handled ~50 product change notifications/year and second source proposals for component substitution without performance loss.
• Coordinate technical deliverables with international teams across Germany, China, India, Mexico, and Romania.
• KEY ACHIEVEMENTS:
• Designed high-current power stages (up to 100A on 12V/24V nets), integrating input capacitor banks, reverse battery protection, and soft-start/sequencing circuits for 6-MOSFET H-bridges.
• Successfully conducted first-power prototype bring-ups: performed offline impedance checks, limited-current power-ups, and validated power sequencing, clock stability, and signal integrity.
• Maintained an exceptional production quality with a defect rate of under 100 PPM across all projects.
• ENVIRONMENT:
• Cadence, Altium Designer, PCB Investigator, SPI, I2C, CAN, ISO 26262, Power Electronics (Buck/Boost, PMIC, High Current 100A).
• Oscilloscope, VNA, LCR meter, thermal camera

CONTEXT:

• Hardware optimization, EMC qualification, and advanced root-cause analysis for automotive systems and customized client subsystems.
• MAIN MISSIONS:
• Design complete electronic architectures from strict client specifications and requirements.
• Define, execute, and document comprehensive thermal and EMC test plans in accordance with ISO 7637-2.
• Develop analog circuits, including robust watchdog mechanisms using discrete components for MCU reset management.
• KEY ACHIEVEMENTS:
• Resolved a critical SPI communication failure during EMC qualification: characterized the signal integrity vs. synchronization via oscilloscope, identified a faulty capacitor, and validated the fix in an anechoic chamber to achieve ISO 26262 safety compliance.
• Optimized capacitive decoupling to ensure large current spikes did not disrupt the main system architecture.
• ENVIRONMENT:
• Oscilloscope, VNA, Thermal Camera, Anechoic Chamber, PSpice, ISO 7637-2, Analog/Mixed-Signal Design, SPI.